RL78/G1H CHAPTER 8 TIMER RJ
R01UH0575EJ0120 Rev. 1.20 Page 228 of 920
Dec 22, 2016
8.3.3 Timer RJ counter register 0 (TRJ0)
TRJ0 is a 16-bit register. The write value is written to the reload register and the read value is read from the
counter.
The states of the reload register and the counter are changed depending on the TSTART bit in the TRJCR0
register. For details, see 8.4.1 Reload Register and Counter Rewrite Operation.
The TRJ0 register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to FFFFH.
Figure 8 - 4 Format of Timer RJ counter register 0 (TRJ0)
Note 1. When 1 is written to the TSTOP bit in the TRJCR0 register, the 16-bit counter is forcibly stopped and set to
FFFFH.
Note 2. When the setting of bits TCK2 to TCK0 in the TRJMR0 register is other than 001B (fCLK/8) or 011B (fCLK/2), if
the TRJ0 register is set to 0000H, a request signal to the DTC and the ELC is generated only once
immediately after the count starts. starts.
When the TRJ0 register is set to 0000H or a higher value, a request signal is generated each time TRJ
underflows.
Caution When the TRJ0 register is accessed, the CPU does not proceed to the next instruction processing
but enters the wait state for CPU processing. For this reason, if this wait state occurs, the number of
instruction execution clocks is increased by the number of wait clocks. The number of wait clocks for
access to the TRJ0 register is one clock for both writing and reading.
Address: F0500H After Reset: FFFFH R/W
1
Symbol1514131211109876543210
TRJ0
— Function Setting Range
Bits 15 to 0
16-bit counter
Notes 1, 2
0000H to FFFFH
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