RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS
R01UH0575EJ0120 Rev. 1.20 Page 728 of 920
Dec 22, 2016
19.4.4 Interrupt servicing during division instruction
The RL78/G1H handles interrupts during the DIVHU/DIVWU instruction in order to enhance the interrupt
response when a division instruction is executed.
• When an interrupt is generated while the DIVHU/DIVWU instruction is executed, the instruction is suspended
• After the instruction is suspended, the PC indicates the next instruction after DIVHU/DIVWU
• An interrupt is generated by the next instruction
• PC-3 is stacked to execute the DIVHU/DIVWU instruction again
Normal interrupt Interrupts while Executing DIVHU/DIVWU Instruction
(SP-1)
← PSW (SP-1) ← PSW
(SP-2)
← (PC)S (SP-2) ← (PC-3)S
(SP-3) ← (PC)H (SP-3) ← (PC-3)H
(SP-4) ← (PC)L (SP-4) ← (PC-3)L
PCS ← 0000 PCS ← 0000
PC
H ← (Vector) PCH ← (Vector)
PC
L ← (Vector) PCL ← (Vector)
SP
← SP-4 SP ← SP-4
IE
← 0IE ← 0
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