RL78/G1H CHAPTER 10 12-BIT INTERVAL TIMER
R01UH0575EJ0120 Rev. 1.20 Page 264 of 920
Dec 22, 2016
10.3.3 12-bit interval timer control register (ITMC)
This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the
timer compare value.
The ITMC register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0FFFH.
Figure 10 - 4 Format of 12-bit interval timer control register (ITMC)
Caution 1. Before changing the RINTE bit from 1 to 0, use the interrupt mask flag register to disable the INTIT
interrupt servicing. When the operation starts (from 0 to 1) again, clear the ITIF flag, and then enable
the interrupt servicing.
Caution 2. The value read from the RINTE bit is applied one count clock cycle after setting the RINTE bit.
Caution 3. When setting the RINTE bit after returned from standby mode and entering standby mode again,
confirm that the written value of the RINTE bit is reflected, or wait that more than one clock of the
count clock has elapsed after returned from standby mode. Then enter standby mode.
Caution 4. Only change the setting of the ITCMP11 to ITCMP0 bits when RINTE = 0.
However, it is possible to change the settings of the ITCMP11 to ITCMP0 bits at the same time as
when changing RINTE from 0 to 1 or 1 to 0.
Address: FFF90H After reset: 0FFFH R/W
Symbol 15 14 13 12 11 to 0
ITMC RINTE 0 0 0 ITCMP11 to ITCMP0
RINTE 12-bit interval timer operation control
0 Count operation stopped (count clear)
1 Count operation started
ITCMP11 to ITCMP0 Specification of the 12-bit interval timer compare value
001H These bits generate a fixed-cycle interrupt (count clock cycles x (ITCMP setting + 1)).
•
•
•
FFFH
000H Setting prohibit
Example interrupt cycles when 001H or FFFH is specified for ITCMP11 to ITCMP0
• ITCMP11 to ITCMP0 = 001H, count clock: when f
SUB = 32.768 kHz
1/32.768 [kHz]
× (1 + 1) = 0.06103515625 [ms] ≅ 61.03 [μs]
• ITCMP11 to ITCMP0 = FFFH, count clock: when f
SUB = 32.768 kHz
1/32.768 [kHz]
× (4095 + 1) = 125 [ms]
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