RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 441 of 920
Dec 22, 2016
Figure 15 - 12 Format of IICA status register n (IICSn) (3/3)
Remark 1. LRELn: Bit 6 of IICA control register n0 (IICCTLn0)
IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
Remark 2. n = 0, 1
15.3.4 IICA flag register n (IICFn)
This register sets the operation mode of I
2
C and indicates the status of the I
2
C bus.
The IICFn register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STTn clear flag
(STCFn) and I
2
C bus status flag (IICBSYn) bits are read-only.
The IICRSVn bit can be used to enable/disable the communication reservation function.
The STCENn bit can be used to set the initial value of the IICBSYn bit.
The IICRSVn and STCENn bits can be written only when the operation of I
2
C is disabled (bit 7 (IICEn) of IICA
control register n0 (IICCTLn0) = 0). When operation is enabled, the IICFn register can be read.
Reset signal generation clears this register to 00H.
ACKDn Detection of acknowledge (ACK)
0 Acknowledge was not detected.
1 Acknowledge was detected.
Condition for clearing (ACKDn = 0) Condition for setting (ACKDn = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LRELn = 1 (exit from communications)
• When the IICEn bit changes from 1 to 0 (operation stop)
• Reset
• After the SDAAn line is set to low level at the rising edge
of SCLAn line’s ninth clock
STDn Detection of start condition
0 Start condition was not detected.
1 Start condition was detected. This indicates that the address transfer period is in effect.
Condition for clearing (STDn = 0) Condition for setting (STDn = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock following
address transfer
• Cleared by LRELn = 1 (exit from communications)
• When the IICEn bit changes from 1 to 0 (operation stop)
• Reset
• When a start condition is detected
SPDn Detection of stop condition
0 Stop condition was not detected.
1 Stop condition was detected. The master device’s communication is terminated and the bus is released.
Condition for clearing (SPDn = 0) Condition for setting (SPDn = 1)
• At the rising edge of the address transfer byte’s first clock
following setting of this bit and detection of a start
condition
• When the WUPn bit changes from 1 to 0
• When the IICEn bit changes from 1 to 0 (operation stop)
• Reset
• When a stop condition is detected
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