RL78/G1H CHAPTER 13 A/D CONVERTER
R01UH0575EJ0120 Rev. 1.20 Page 300 of 920
Dec 22, 2016
13.3.8 Conversion result comparison upper limit setting register (ADUL)
This register is used to specify the setting for checking the upper limit of the A/D conversion results.
The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is
controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure
13 - 9).
The ADUL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Caution 1.When 10-bit resolution A/D conversion is selected, the higher eight bits of the 10-bit A/D
conversion result register (ADCR) are compared with the ADUL and ADLL registers.
Caution 2. Only write new values to the ADUL and ADLL registers while conversion is stopped (ADCS =
0, ADCE = 0).
Caution 3. The setting of the ADUL and ADLL registers must be greater than that of the ADLL register.
Figure 13 - 13 Format of Conversion result comparison upper limit setting register (ADUL)
13.3.9 Conversion result comparison lower limit setting register (ADLL)
This register is used to specify the setting for checking the lower limit of the A/D conversion results.
The A/D conversion results and ADLL register value are compared, and interrupt signal (INTAD) generation is
controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure
13 - 9).
The ADLL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13 - 14 Format of Conversion result comparison lower limit setting register (ADLL)
Caution 1. When 10-bit resolution A/D conversion is selected, the higher eight bits of the 10-bit A/D conversion
result register (ADCR) are compared with the ADUL and ADLL registers.
Caution 2. Only write new values to the ADUL and ADLL registers while conversion is stopped (ADCS = 0, ADCE
= 0).
Caution 3. The setting of the ADUL and ADLL registers must be greater than that of the ADLL register.
Address: F0011H After reset: FFH R/W
Symbol76543210
ADUL ADUL7 ADUL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADUL0
Address: F0012H After reset: 00H R/W
Symbol76543210
ADLL ADLL7 ADLL6 ADLL5 ADLL4 ADLL3 ADLL2 ADLL1 ADLL0
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