RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 211 of 920
Dec 22, 2016
7.8.5 Operation as delay counter
It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and
then generate INTTMmn (a timer interrupt) after any specified interval.
It can also generate INTTMmn (timer interrupt) at any interval by making a software set TSmn = 1 and the count
down start during the period of TEmn = 1.
The interrupt generation period can be calculated by the following expression.
Timer count register mn (TCRmn) operates as a down counter in the one-count mode.
When the channel start trigger bit (TSmn, TSHm1, TSHm3) of timer channel start register m (TSm) is set to 1,
the TEmn, TEHm1, TEHm3 bits are set to 1 and the TImn pin input valid edge detection wait status is set.
Timer count register mn (TCRmn) starts operating upon TImn pin input valid edge detection and loads the value
of timer data register mn (TDRmn). The TCRmn register counts down from the value of the TDRmn register it
has loaded, in synchronization with the count clock. When TCRmn = 0000H, it outputs INTTMmn and stops
counting until the next TImn pin input valid edge is detected.
The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the
next period.
Figure 7 - 59 Block Diagram of Operation as Delay Counter
Note For using channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Remark m: Unit number (m = 0), n: Channel number (n = 3)
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
Interrupt
controller
Interrupt signal
(INTTMmn)
Timer data
register mn (TDRmn)
Operation clock
Note
CKm0
CKm1
Timer counter
register mn (TCRmn)
Edge
detection
TSmn
Clock selectionTrigger selection
TImn pin
Noise
filter
TNFENxx
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