RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 210 of 920
Dec 22, 2016
Figure 7 - 58 Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
Remark m: Unit number (m = 0), n: Channel number (n = 3)
Software Operation Hardware Status
TAU
default
setting
Input clock supply for timer array unit m is stopped
(Clock supply is stopped and writing to each register
is disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1. Input clock supply for timer array unit m is supplied.
Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 to CKm3.
Channel
default
setting
Sets the corresponding bit of the noise filter enable
register 1 (NFEN1) to 0 (off) or 1 (on).
Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
Clears the TOEmn bit to 0 and stops operation of TOmn.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Operation is resumed.
Operation
start
Sets the TSmn bit to 1.
The TSmn bit automatically returns to 0 because it is
a trigger bit.
TEmn = 1, and the TImn pin start edge detection wait
status is set.
Detects the TImn pin input count start valid edge. Clears timer count register mn (TCRmn) to 0000H and
starts counting up.
During
operation
Set value of the TDRmn register can be changed.
The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TMRmn register, TOMmn, TOLmn,
TOmn, and TOEmn bits cannot be changed.
When the TImn pin start edge is detected, the counter
(TCRmn) counts up from 0000H. If a capture edge of the
TImn pin is detected, the count value is transferred to
timer data register mn (TDRmn) and INTTMmn is
generated.
If an overflow occurs at this time, the OVF bit of timer
status register mn (TSRmn) is set; if an overflow does
not occur, the OVF bit is cleared. The TCRmn register
stops the count operation until the next TImn pin start
edge is detected.
Operation
stop
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is
a trigger bit.
TEmn = 0, and count operation stops.
The TCRmn register holds count value and stops.
The OVF bit of the TSRmn register is also held.
TAU
stop
The TAUmEN bit of the PER0 register is cleared to 0. Input clock supply for timer array unit m is stopped
All circuits are initialized and SFR of each channel is
also initialized.
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