RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 209 of 920
Dec 22, 2016
Figure 7 - 57 Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width
(a) Timer mode register mn (TMRmn)
(b) Timer output register m (TOm)
(c) Timer output enable register m (TOEm)
(d) Timer output level register m (TOLm)
(e) Timer output mode register m (TOMm)
Note TMRm2: MASTERmn bit
TMRm1, TMRm3: SPLITmn bit
TMRm0: Fixed to 0
Remark m: Unit number (m = 0), n: Channel number (n = 3)
1514131211109876543210
TMRmn
CKSmn1
1/0
CKSmn0
00
CCSmn
0
M/S
Note
0
STSmn2
0
STSmn1
1
STSmn0
0
CISmn1
1
CISmn0
1/0 0 0
MDmn3
1
MDmn2
1
MDmn1
0
MDmn0
0
Operation mode of channel n
110B: Capture & one-count
Setting of operation when counting is started
0: Does not generate INTTMmn when
counting is started.
Selection of TImn pin input edge
10B: Both edges (to measure low-level width)
11B: Both edges (to measure high-level width)
Start trigger selection
010B: Selects the TImn pin input valid edge.
Setting of MASTERmn bit (channel 2)
0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3)
0: 16-bit timer mode
Count clock selection
0: Selects operation clock (f
MCK).
Operation clock (f
MCK) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
Bit n
TOm
TOmn
0
0: Outputs 0 from TOmn.
Bit n
TOEm
TOEmn
0
0: Stops the TOmn output operation by counting operation.
Bit n
TOLm
TOLmn
0
0: Cleared to 0 when master channel output mode (TOMmn = 0)
Bit n
TOMm
TOMmn
0
0: Sets master channel output mode.
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