RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 208 of 920
Dec 22, 2016
Figure 7 - 55 Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
Note For channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Figure 7 - 56 Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement
Remark 1. m: Unit number (m = 0), n: Channel number (n = 3)
Remark 2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm)
TImn: TImn pin input signal
TCRmn: Timer count register mn (TCRmn)
TDRmn: Timer data register mn (TDRmn)
OVF: Bit 0 of timer status register mn (TSRmn)
Interrupt
controller
Interrupt signal
(INTTMmn)
Timer data
register mn (TDRmn)
Operation clock
Note
CKm0
CKm1
Edge
detection
Timer counter
register mn (TCRmn)
Clock selectionTrigger selection
TImn pin
Noise
filter
TNFENxx
TSmn
TEmn
TImn
TDRmn
TCRmn
b
0000H
a
c
INTTMmn
b
a
c
OVF
FFFFH
0000H
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