RL78/G1H CHAPTER 8 TIMER RJ
R01UH0575EJ0120 Rev. 1.20 Page 235 of 920
Dec 22, 2016
8.5.5 When Timer RJ Operating Clock is Stopped
Supplying or stopping the timer RJ clock can be controlled by the TRJ0EN bit in the PER1 register. Note that the
following SFRs cannot be accessed while the timer RJ clock is stopped. Make sure the timer RJ clock is supplied
before accessing any of these registers.
Registers TRJ0, TRJCR0, and TRJMR0.
8.5.6 When Count is Forcibly Stopped by TSTOP Bit
After the counter is forcibly stopped by the TSTOP bit in the TRJCR0 register, do not access the following SFRs
for one cycle of the count source.
Registers TRJ0, TRJCR0, and TRJMR0
8.5.7 When Selecting fIL as Count Source
When selecting fIL as the count source, set the WUTMMCK0 bit in the subsystem clock supply mode control
register (OSMC) to 1. However, f
IL cannot be selected as the count source for timer RJ when fSUB is selected as
the count source for the real-time clock or the 12-bit interval timer.
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