RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 339 of 920
Dec 22, 2016
14.3.5 Serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n.
Bits 7 to 0 (lower 8 bits) function as a transmit/receive buffer register, and bits 15 to 9 (higher 7 bits) are used as
a register that sets the division ratio of the operation clock (f
MCK).
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock
by the higher 7 bits of the SDRmn register is used as the transfer clock.
If the CCSmn bit of serial mode register mn (SMRmn) is set to 1, set bits 15 to 9 (upper 7 bits) to 0000000B. The
input clock f
SCK (slave transfer in CSI mode) from the SCKp pin is used as the transfer clock.
The lower 8 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the
parallel data converted by the shift register is stored in the lower 8 bits, and during transmission, the data to be
transmitted to the shift register is set to the lower 8 bits.
The SDRmn register can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During
operation (SEmn = 1), a value is written only to the lower 8 bits of the SDRmn register. When the SDRmn register
is read during operation, the higher 7 bits are always read as 0.
Reset signal generation clears the SDRmn register to 0000H.
Figure 14 - 10 Format of Serial data register mn (SDRmn)
Caution 1. Be sure to clear bit 8 to “0”.
Caution 2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
Caution 3. When operation is stopped (SEmn = 0), do not rewrite SDRmn [7:0] by an 8-bit memory manipulation
instruction (SDRmn [15:9] are all cleared to 0).
Remark
For the function of the lower 8 bits of the SDRmn register, see 14.2 Configuration of Serial Array Unit.
Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03) After reset: 0000H R/W
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11)
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13)
FFF45H (SDR02) FFF44H (SDR02)
Symbol1514131211109876543210
SDRmn 0
SDRmn[15:9] Transfer clock set by dividing the operating clock
0000000
fMCK/2
0000001
fMCK/4
0000010
fMCK/6
0000011
fMCK/8
1111110
fMCK/254
1111111
fMCK/256
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