RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 338 of 920
Dec 22, 2016
Figure 14 - 9 Format of Serial communication operation setting register mn (SCRmn) (2/2)
Note 1. The SCR02 and SCR12 registers only.
Note 2. 0 is always added regardless of the data contents.
Caution Be sure to clear bits 3, 6, and 11 to “0” (Also clear bit 5 of the SCR03, SCR10, SCR11, or SCR13
register to 0). Be sure to set bits 2 and 1 to “1”.
Address: F011CH, F011DH (SCR02), F011EH, F011FH (SCR03), After reset: 0087H R/W
F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13)
Symbol1514131211109876543210
SCRmn
TXE
mn
RXE
mn
DAP
mn
CKP
mn
0
EOC
mn
PTC
mn1
PTC
mn0
DIR
mn
0
SLC
mn1
Note 1
SLC
mn0
011
DLS
mn0
PTC
mn1
PTC
mn0
Setting of parity bit in UART mode
Transmission Reception
0 0 Does not output the parity bit. Receives without parity
01
Outputs 0 parity
Note 2
.
No parity judgment
1 0 Outputs even parity. Judged as even parity.
1 1 Outputs odd parity. Judges as odd parity.
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode.
DIR
mn
Selection of data transfer sequence in CSI and UART modes
0 Inputs/outputs data with MSB first.
1 Inputs/outputs data with LSB first.
SLC
mn1
Note 1
SLC
mn0
Setting of stop bit in UART mode
0 0 No stop bit
0 1 Stop bit length = 1 bit
1 0 Stop bit length = 2 bits (mn = 02, 10, 12 only)
1 1 Setting prohibited
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely
transferred.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception.
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) or 2 bits (SLCmn1, SLCmn0 = 1, 0) during UART transmission.
DLS
mn0
Setting of data length in CSI and UART modes
0 7-bit data length (stored in bits 0 to 6 of the SDRmn register)
1 8-bit data length (stored in bits 0 to 7 of the SDRmn register)
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