RL78/G1H CHAPTER 23 VOLTAGE DETECTOR
R01UH0575EJ0120 Rev. 1.20 Page 773 of 920
Dec 22, 2016
23.5 Cautions for Voltage Detector
(1) Voltage fluctuation when power is supplied
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVD detection
voltage, the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following
action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 23 - 9 Example of Software Processing If Supply Voltage Fluctuation is 50 ms or Less in Vicinity of LVD
Detection Voltage
Note If reset is generated again during this period, initialization processing <2> is not started.
Remark m = 0, 1
n = 0 to 3
Reset
Yes
No
Setting timer array unit
(to measure 50 ms)
Clearing WDT
50 ms have passed?
(TMIFmn = 1?)
Initialization processing <1>
Initialization processing <2>
; e.g. fCLK = High-speed on-chip oscillator clock (4.04 MHz (MAX.))
Source: f
MCK = (4.04 MHz (MAX.))/2
8
,
where comparison value = 789:
≈ 50 ms
Timer starts (TSmn = 1).
; Initial setting for port.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Note
Refer to Figure 21 - 5 Procedure for Checking Reset Source.
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