RL78/G1H CHAPTER 23 VOLTAGE DETECTOR
R01UH0575EJ0120 Rev. 1.20 Page 774 of 920
Dec 22, 2016
(2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released
There is some delay from the time supply voltage (V
DD) < LVD detection voltage (VLVD) until the time LVD reset
has been generated.
In the same way, there is also some delay from the time LVD detection voltage (V
LVD) ≤ supply voltage (VDD)
until the time LVD reset has been released. For details, see 31.6.3 LVD characteristics.
(3) Power on when LVD is off
Use the external reset input via the RESET
pin when the LVD is off.
For an external reset, input a low level for 10 μs or more to the RESET pin. To perform an external reset upon
power application, input a low level to the RESET
pin, turn power on, continue to input a low level to the pin for
10 μs or more within the operating voltage range shown in 31.4 AC Characteristics, and then input a high level
to the pin.
(4) Operating voltage fall when LVD is off or LVD interrupt mode is selected
When the operating voltage falls with the LVD is off or with the LVD interrupt mode is selected, this LSI should
be placed in the STOP mode, or placed in the reset state by controlling the externally input reset signal, before
the voltage falls below the operating voltage range defined in 31.4 AC Characteristics. When restarting the
operation, make sure that the operation voltage has returned within the range of operation.
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