RL78/G1H CHAPTER 13 A/D CONVERTER
R01UH0575EJ0120 Rev. 1.20 Page 295 of 920
Dec 22, 2016
13.3.3 A/D converter mode register 1 (ADM1)
This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal.
The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13 - 6 Format of A/D converter mode register 1 (ADM1)
Caution 1. Rewrite the value of the ADM1 register while conversion is stopped (ADCS = 0, ADCE = 0).
Caution 2. To complete A/D conversion, specify at least the following time as the hardware trigger interval:
Hardware trigger no wait mode: 2 f
CLK clock + conversion start time + A/D conversion time
Hardware trigger wait mode: 2 f
CLK clock + conversion start time + A/D power supply stabilization
wait time + A/D conversion time
Caution 3. In modes other than SNOOZE mode, input of the next INTRTC or INTIT will not be recognized as a
valid hardware trigger for up to four f
CLK cycles after the first INTRTC or INTIT is input.
Remark
fCLK: CPU/peripheral hardware clock frequency
Address: FFF32H After reset: 00H R/W
Symbol76543210
ADM1 ADTMD1 ADTMD0 ADSCM 0 0 0 ADTRS1 ADTRS0
ADTMD1 ADTMD0 Selection of the A/D conversion trigger mode
0 0 Software trigger mode
01
1 0 Hardware trigger no-wait mode
1 1 Hardware trigger wait mode
ADSCM Specification of the A/D conversion mode
0 Sequential conversion mode
1 One-shot conversion mode
ADTRS1 ADTRS0 Selection of the hardware trigger signal
0 0 End of timer channel 1 count or capture interrupt signal (INTTM01)
0 1 Event signal selected by ELC
1 0 Real-time clock interrupt signal (INTRTC)
1 1 12-bit interval timer interrupt signal (INTIT)
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