RL78/G1H CHAPTER 23 VOLTAGE DETECTOR
R01UH0575EJ0120 Rev. 1.20 Page 772 of 920
Dec 22, 2016
Note 1. The LVIMK flag is set to “1” by reset signal generation.
Note 2. After an interrupt is generated, perform the processing according to Figure 23 - 8 Setting Procedure for Operating Voltage
Check and Reset in interrupt and reset mode.
Note 3. After reset is released, perform the processing according to Figure 23 - 8 Setting Procedure for Operating Voltage Check
and Reset in interrupt and reset mode.
Remark V
POR: POR power supply rise detection voltage
V
PDR: POR power supply fall detection voltage
Figure 23 - 8 Setting Procedure for Operating Voltage Check and Reset
INTLVI generated
No
Save processing
LVISEN = 1
Perform required save processing.
LVILV = 0
LVIOMSK = 0
No
LVISEN = 1
LVIMD = 0
Yes
LVISEN = 0
LVD reset generated
Yes
LVISEN = 0
Normal operation
Internal reset by LVD
is generated
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1).
Set the LVILV bit to 0 to set the high-voltage detection
level (V
LVDH).
Set the LVISEN bit to 0 to enable voltage detection.
When an internal reset by voltage detector (LVD) is not
generated, a condition of V
DD becomes VDD ≥ VLVDH.
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1).
Set the LVIMD bit to 0 to set interrupt mode.
Set the LVISEN bit to 0 to enable voltage detection.
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