RL78/G1H CHAPTER 23 VOLTAGE DETECTOR
R01UH0575EJ0120 Rev. 1.20 Page 771 of 920
Dec 22, 2016
Figure 23 - 7 Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
(Notes and Remark are listed on the next page.)
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2)
LVIF flag
LVIOMSK flag
Operation status
LVIIF flag
INTLVI
LVIMD flag
LVIRF flag
LVILV flag
Internal reset
signal
POR reset signal
LVD reset signal
Supply voltage (VDD)
V
LVDL
VPOR = 1.51 V (TYP.)
V
PDR = 1.50 V (TYP.)
V
LVDH
LVIMK flag
(set by software)
LVISEN flag
(set by software)
Save
processing
RESET
Normal
operation
RESET
Normal
operation
RESET
Cleared by
software
Cleared by software
H
Note 1
Time
Save
processing
Cleared
When a condition of V
DD
is V
DD
< V
LVDH
after releasing the mask,
a reset is generated because of LVIMD = 1 (reset mode).
Cleared by
software
Note 2
Cleared by
software
Note 3
Cleared
Wait for stabilization by software (400 µs or 5 clocks of f
IL
)
Note 3
Lower limit of operation voltage
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