RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 342 of 920
Dec 22, 2016
Figure 14 - 13 Format of Serial status register mn (SSRmn) (2/2)
Note The SSR03 and SSR13 registers only.
Caution If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the
register is discarded and an overrun error (OVEmn = 1) is detected.
Address: F0104H, F0105H (SSR02), F0106H, F0107H (SSR03), After reset: 0000H R
F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13)
Symbol1514131211109876543210
SSRmn000000000
TSF
mn
BFF
mn
00
FEF
mn
Note
PEF
mn
OVF
mn
FEF
mn
Note
Framing error detection flag of channel n
0 No error occurs.
1 An error occurs (during UART reception).
<Clear condition>
• 1 is written to the FECTmn bit of the SIRmn register.
<Set condition>
• A stop bit is not detected when UART reception ends.
PEF
mn
Parity error detection flag of channel n
0 No error occurs.
1 An error occurs (during UART reception).
<Clear condition>
• 1 is written to the PECTmn bit of the SIRmn register.
<Set condition>
• The parity of the transmit data and the parity bit do not match when UART reception ends (parity error).
OVF
mn
Overrun error detection flag of channel n
0 No error occurs.
1 An error occurs
<Clear condition>
• 1 is written to the OVCTmn bit of the SIRmn register.
<Set condition>
• Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next receive
data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and reception mode in
each communication mode).
• Transmit data is not ready for slave transmission or transmission and reception in CSI mode.
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