RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 455 of 920
Dec 22, 2016
Figure 15 - 26 Wait (2/2)
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKEn = 1)
Remark ACKEn: Bit 2 of IICA control register n0 (IICCTLn0)
WRELn: Bit 5 of IICA control register n0 (IICCTLn0)
A wait may be automatically generated depending on the setting of bit 3 (WTIMn) of IICA control register n0
(IICCTLn0).
Normally, the receiving side cancels the wait state when bit 5 (WRELn) of the IICCTLn0 register is set to 1 or
when FFH is written to the IICA shift register n (IICAn), and the transmitting side cancels the wait state when data
is written to the IICAn register.
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STTn) of the IICCTLn0 register to 1
• By setting bit 0 (SPTn) of the IICCTLn0 register to 1
Remark n = 0, 1
IICAn
SCLAn
IICAn
SCLAn
ACKEn
SCLAn
SDAAn
H
Generate according to previously set ACKEn value
6789
123
D2 ACKD1 D0 D7 D6 D5
Wait from slave
Wait from master and slave
FFH is written to IICAn or
WRELn is set to 1
IICAn data write (cancel wait)
6789 1 23
Master and slave both wait
after output of ninth clock
Master
Slave
Transfer lines
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