RL78/G1H CHAPTER 6 CLOCK GENERATOR
R01UH0575EJ0120 Rev. 1.20 Page 130 of 920
Dec 22, 2016
Tables 6 - 3 to 6 - 7 show transition of the CPU clock and examples of setting the SFR registers.
Table 6 - 3 CPU Clock Transition and SFR Register Setting Examples (1/5)
(1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)
Note 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction
after reset release.
Note 2. Set the oscillation stabilization time as follows.
• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤ Oscillation
stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 31
ELECTRICAL SPECIFICATIONS).
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction
after reset release.
Remark 1. ×: Don’t care
Remark 2. (A) to (J) in Tables 6 - 3 to 6 - 7 correspond to (A) to (J) in Figure 6 - 19.
Status Transition SFR Register Setting
(A)
→ (B) SFR registers do not have to be set (default status after reset release).
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note 1
OSTS
Register
CSC
Register
OSTC
Register
CKC
Register
Status Transition EXCLK OSCSEL AMPH MSTOP MCM0
(A)
→ (B) → (C)
(X1 clock: 1 MHz
≤ fX ≤ 10 MHz)
010
Note 2 0
Must be
checked
1
(A)
→ (B) → (C)
(X1 clock: 10 MHz
< fX ≤ 20 MHz)
011
Note 2 0
Must be
checked
1
(A)
→ (B) → (C)
(external main clock)
11
× Note 2 0
Must not be
checked
1
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register
Note
CSC
Register
Waiting for
Oscillation
Stabilization
CKC
Register
Status Transition EXCLKS OSCSELS AMPHS1 AMPHS0 XTSTOP CSS
(A)
→ (B) → (C)
(XT1 clock)
0 1 0/1 0/1 0 Necessary 1
(A)
→ (B) → (C)
(external sub clock)
11
××0 Necessary 1
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