RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 362 of 920
Dec 22, 2016
(4) Processing flow (in continuous transmission mode)
Figure 14 - 30 Timing Chart of Master Transmission (in Continuous Transmission Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data
is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the transfer end
interrupt of the last transmit data.
Transmit data 2Transmit data 1
Transmit data 3
Transmit data 2
<1>
<2> <2><2><3> <3> <3> <5>
<6>
<4>
Note
Transmit data 3
SSmn
SEmn
SDRmn
SCKp pin
SOp pin
Shift register mn
INTCSIp
TSFmn
BFFmn
MDmn0
STmn
Transmit data 1
Data transmissionData transmissionData transmission
Shift operation
Shift operation Shift operation
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