Renesas RL78/G1H User Manual

RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 473 of 920
Dec 22, 2016
Figure 15 - 36 Master Operation in Multi-Master System (2/3)
Note The wait time is calculated as follows.
(IICWLn setting value + IICWHn setting value + 4) / f
MCK + tF × 2
Remark1. IICWLn: IICA low-level width setting register n
IICWHn: IICA high-level width setting register n
t
F: SDAAn and SCLAn signal falling times
f
MCK: IICA operating clock frequency
Remark2. n = 0, 1
A
STTn = 1
Wait
Slave operation
Yes
MSTSn = 1?
EXCn = 1 or COIn =1?
Prepares for starting communication
(generates a start condition).
Waits for bus release
(communication being reserved).
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
No
INTIICAn
interrupt occurs?
Yes
Yes
No
No
C
Enables reserving communication.
Secure wait time
Note
by software.
Communication processing
Communication processing
B
STTn = 1
Wait
Slave operation
Yes
IICBSYn = 0?
EXCn = 1 or COIn =1?
Prepares for starting communication
(generates a start condition).
Disables reserving communication.
Waits for bus release
Detects a stop condition.
No
No
INTIICAn
interrupt occurs?
Yes
Yes
No
Yes
STCFn = 0?
No
D
C
D
Wait for 5 fMCK clocks.

Renesas RL78/G1H Specifications

General

Brand	Renesas
Model	RL78/G1H
Category	Microcontrollers
Language	English