RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 504 of 920
Dec 22, 2016
Figure 15 - 42 Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4)
(3) Data ~ data ~ stop condition
Note 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master device.
Note 2. Make sure that the time between the rise of the SCLAn pin signal and the generation of the stop condition after a stop
condition has been issued is at least 4.0
μs when specifying standard mode and at least 0.6 μs when specifying fast
mode.
Note 3. For releasing wait state during reception of a slave device, write “FFH” to IICAn or set the WRELn bit.
Remark n = 0, 1
ACKDn
(ACK detection)
IICAn
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
STTn
(ST trigger)
SPTn
(SP trigger)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
Bus line
TRCn
(transmit/receive)
Master side
SCLAn (bus)
(clock line)
SDAAn (bus)
(data line)
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
D166D165D164D163D162D161
Note 3
ACK
<9>
<11>
<12>
<13>
D167
Note 1
D160
ACK
Note 3<10>
<8>
<7>
D150
Note 2
<14>
<15>
Stop condition
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
H
H
L
H
H
L
L
L
L
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