RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 506 of 920
Dec 22, 2016
Figure 15 - 43 Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4)
(4) Data ~ restart condition ~ address
Note 1. Make sure that the time between the rise of the SCLAn pin signal and the generation of the start condition after a
restart condition has been issued is at least 4.7
μs when specifying standard mode and at least 0.6 μs when
specifying fast mode.
Note 2. For releasing wait state during reception of a slave device, write “FFH” to IICAn or set the WRELn bit.
Remark n = 0, 1
ACKDn
(ACK detection)
IICAn
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
STTn
(ST trigger)
SPTn
(SP trigger)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
Bus line
TRCn
(transmit/receive)
Master side
SCLAn (bus)
(clock line)
SDAAn (bus)
(data line)
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
D12D11 D10AD6
Slave address
Restart condition
<7>
<8>
<iii>
D13
AD5 AD4 AD3 AD2 AD1
ACK
<ii>
<i> Note 2
Note 1
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
H
H
L
L
H
H
L
L
H
H
L
To Next Page
Loading...
Need help?
General
