RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 578 of 920
Dec 22, 2016
(12) CSMA control register 0 (BBCSMACON0)
This register controls the CSMA-CA operation.
Setting “1” to the automatic CSMA-CA start bit starts the CSMA-CA operation. Be sure to set this bit under
the state it is IDLE. Note that these bits are automatically cleared to “0” upon completion of the CSMA-CA
operation. In addition, setting “0” also disables writing.
Stop the CSMA-CA operation by using the RF communication stop bit when you want to stop the CSMA-CA
operation.
Setting “1” to the transmit after automatic CSMA-CA bit automatically performs the transmission process if
it's okay after the completion of the CSMA-CA operation.
Setting “1” to the reception during CSMA-CA function enable bit enables the reception during the wait time
for the CCA operation in the CSMA-CA operation.
The back off period count stops during a frame reception.
The unicast frame bit sets the unicast frame value. Setting “1” to the unicast frame enable bit enables the
function.
The BBCSMACON0 register consists of 8 bits and can be accessed (serial interface communication) in 8 bit
unit.
Reset signal generation clears this register to 00H.
Figure 18 - 18 CSMA Control Register 0 (BBCSMACON0) Format
Note Bit 0 is Write Only.
Caution Be sure to clear bits 3, 5 to 7 to “0”.
Address:
000DH
After reset:
00H
R/W
Note
Symbol76543210
BBCSMA
CON0
0 0 0 UNICASTFR
M
0 CSMARCVEN CSMATRNST CSMAST
UNICASTFRM
Unicast frame bit
0 Unicast frame value = 0
1 Unicast frame value = 1
CSMARCVEN
Reception during CSMA-CA function enable bit
0 Receive function disabled
1 Receive function enabled
CSMATRNST
Transmit after automatic CSMA-CA bit
0 Nothing performed
1 Transmit after CSMA-CA process
CSMAST Automatic CSMA-CA start bit
0 Nothing performed
1 Automatic CSMA-CA start
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