Renesas RL78/G1H - Page 611

RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 593 of 920
Dec 22, 2016
(26) Baseband interrupt source register 0 (BBINTREQ0)
This register is used to indicate the baseband interrupt source.
This register indicates that “1” is set to the interrupt source corresponding to each interrupt occurrence
timing so that there is an interrupt request. When reading this register, only the bit from which 1 is read is
cleared to 0. Note that perform the dummy read when you clear the bit because writing is disabled.
The BBINTREQ0 register consists of 8 bits and can be accessed (serial interface communication) in 8 bit
unit.
Note
Reset signal generation clears this register to 00H.
Note When reading this register, read 3 bytes of the baseband interrupt source registers 0 to 2
(BBINTREQ0 to BBINTREQ2) continuously (leave SEN internal pin low level).
Figure 18 - 35 Baseband Interrupt Source Register 0 (BBINTREQ0) Format
Caution Bit 6 is X (undefined).
Address:
0036H
After reset: 00H R
Symbol76543210
BBINTREQ0 CCAINTREQ X TRN1INTREQ TRN0INTREQ TRNFININTREQ TIM2INTREQ TIM1INTREQ TIM0INTREQ
CCAINTREQ CCA completion interrupt source bit
0 No request
1 Request exists
TRN1INTREQ Bank 1 transmit completion interrupt source bit
0 No request
1 Request exists
TRN0INTREQ Bank 0 transmit completion interrupt source bit
0 No request
1 Request exists
TRNFININTREQ Frame transmit completion interrupt source bit
0 No request
1 Request exists
TIM2INTREQ Timer compare 2 interrupt source bit
0 No request
1 Request exists
TIM1INTREQ Timer compare 1 interrupt source bit
0 No request
1 Request exists
TIM0INTREQ Timer compare 0 interrupt source bit
0 No request
1 Request exists