Index - 3
6.6 Controlling Clock .................................................................................................................. 124
6.6.1 Example of setting high-speed on-chip oscillator ............................................................. 124
6.6.2 Example of setting X1 oscillation clock ............................................................................. 126
6.6.3 Example of setting XT1 oscillation clock .......................................................................... 128
6.6.4 CPU clock status transition diagram ................................................................................. 129
6.6.5 Condition before changing CPU clock and processing after changing CPU clock ........... 135
6.6.6 Time required for switchover of CPU clock and main system clock ................................. 137
6.6.7 Conditions before clock oscillation is stopped .................................................................. 138
7. TIMER ARRAY UNIT .................................................................................................................. 139
7.1 Functions of Timer Array Unit ............................................................................................... 140
7.1.1 Independent channel operation function .......................................................................... 140
7.1.2 Simultaneous channel operation function ......................................................................... 141
7.1.3 8-bit timer operation function (channels 1 and 3 only) ...................................................... 141
7.2 Configuration of Timer Array Unit ......................................................................................... 142
7.2.1 Timer count register mn (TCRmn) .................................................................................... 146
7.2.2 Timer data register mn (TDRmn) ...................................................................................... 148
7.3 Registers Controlling Timer Array Unit ................................................................................. 149
7.3.1 Peripheral enable register 0 (PER0) ................................................................................. 150
7.3.2 Timer clock select register m (TPSm) ............................................................................... 151
7.3.3 Timer mode register mn (TMRmn) ................................................................................... 154
7.3.4 Timer status register mn (TSRmn) ................................................................................... 159
7.3.5 Timer channel enable status register m (TEm) ................................................................. 160
7.3.6 Timer channel start register m (TSm) ............................................................................... 161
7.3.7 Timer channel stop register m (TTm) ............................................................................... 163
7.3.8 Timer input select register 0 (TIS0) .................................................................................. 164
7.3.9 Timer output enable register m (TOEm) ........................................................................... 165
7.3.10 Timer output register m (TOm) ......................................................................................... 166
7.3.11 Timer output level register m (TOLm) ............................................................................... 167
7.3.12 Timer output mode register m (TOMm) ............................................................................ 168
7.3.13 Noise filter enable register 1 (NFEN1) .............................................................................. 169
7.3.14 Registers controlling port functions of pins to be used for timer I/O ................................. 171
7.4 Basic Rules of Timer Array Unit ............................................................................................ 172
7.4.1 Basic rules of simultaneous channel operation function ................................................... 172
7.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) ............................... 174
7.5 Operation of Counter ............................................................................................................ 175
7.5.1 Count clock (f
TCLK) ........................................................................................................... 175
7.5.2 Start timing of counter ....................................................................................................... 177
7.5.3 Operation of counter ......................................................................................................... 178
7.6 Channel Output (TOmn pin) Control ..................................................................................... 183
7.6.1 TOmn pin output circuit configuration ............................................................................... 183
7.6.2 TOmn Pin Output Setting ................................................................................................. 184
7.6.3 Cautions on Channel Output Operation ........................................................................... 185
7.6.4 Collective manipulation of TOmn bit ................................................................................. 190
7.6.5 Timer Interrupt and TOmn Pin Output at Operation Start ................................................. 191
7.7 Timer Input (TImn) Control ................................................................................................... 192
7.7.1 TImn input circuit configuration ......................................................................................... 192
7.7.2 Noise filter ......................................................................................................................... 192
7.7.3 Cautions on channel input operation ................................................................................ 193
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