Sel 751A - Page 405

10.13
Date Code 20100129 Instruction Manual SEL-751A Relay
Testing and Troubleshooting
Self-Test
CT Board
(power up)
Fail if ID register does not match part
number
Yes Latched
Status Fail
CT Card Fail
CT Board A/D
Offset Warn
Measure dc offset at each input channel –50 mV to
+50 mV
No Not Latched
CT Board A/D Fail Fail if any bits between 15 and 12 are set
or if number of conversions not as
expected
Yes Latched
Status Fail
CT Card Fail
VT Board
(power up)
Fail if ID register does not match part
number
Yes Latched
Status Fail
Volt Card Fail
VT Board A/D
Offset Warn
Measure dc offset at each input channel –50 mV to
+50 mV
No Not Latched
VT Board A/D Fail Fail if any bits between 15 and 12 are set
or if number of conversions not as
expected
Yes Latched
Status Fail
Volt Card Fail
+0.9 V Fail Monitor +0.9 V power supply 0.855 to
0.945 V
Yes Latched Status Fail
+
0.9 V Failure
+1.2 V Fail Monitor +1.2 V power supply 1.152 to
1.248 V
Yes Latched Status Fail
+
1.2 V Failure
+1.5 V Fail Monitor +1.5 V power supply 1.35 to
1.65 V
Yes Latched Status Fail
+
1.5 V Failure
+1.8 V Fail Monitor +1.8 V power supply 1.71 to
1.89 V
Yes Latched Status Fail
+
1.8 V Failure
+3.3 V Fail Monitor +3.3 V power supply 3.07 to
3.53 V
Yes Latched
Status Fail
+3.3 V Failure
+5 V Fail Monitor +5 V power supply 4.65 to
5.35 V
Yes Latched
Status Fail
+5 V Failure
+2.5 V Fail Monitor +2.5 V power supply 2.32 to
2.68 V
Yes Latched
Status Fail
+2.5 V Failure
+3.75 V Fail Monitor +3.75 V power supply 3.48 to
4.02 V
Yes Latched
Status Fail
+3.75 V Failure
–1.25 V Fail Monitor -1.25 V power supply –1.16 to
–1.34 V
Yes Latched
Status Fail
–1.25 V Failure
–5 V Fail Monitor -5 V power supply –4.65 to
–5.35 V
Yes Latched
Status Fail
–5 V Failure
Clock Battery Warn Monitor Clock Battery 2.3 to
3.5 V
No Not Latched
RTC Chip Unable to communicate with clock or
fails time keeping test
No Not Latched
RTC Chip
Internal RAM
Clock chip static RAM fails No Not Latched
Mainboard FPGA
(power up)
Fail if mainboard Field Programmable
Gate Array does not accept program
Yes Latched
Status Fail
FPGA Failure
Mainboard FPGA
(run time)
Fail on lack of data acquisition inter-
rupts
Yes Latched
Status Fail
FPGA Failure
External RTD Fail if no comm, or the external RTD
module reports open RTDs, shorted
RTDs, a power supply failure
NA NA
Table 10.7 Relay Self-Tests (Sheet 2 of 3)
Self-Test Description
Normal
Range
Protection
Disabled
on Failure
Alarm
Status
Front-Panel
Message
on Failure