Stage with Definite-Time Overcurrent Protection, Voltage-Released
Undervoltage Seal-In
Description
Logic of the Stage
[lo_Seal-in_Rel20150215, 2, en_US]
Figure 6-30
Logic Diagram of the Definite-Time Overcurrent Protection, Voltage-Released Undervoltage
Seal-in, Part 1
Signal 4 in the following figure refers to Figure 6-30.
6.4.6
6.4.6.1
Protection and Automation Functions
6.4 Voltage-Dependent Overcurrent Protection, Phases
SIPROTEC 5, Overcurrent Protection, Manual 373
C53000-G5040-C017-8, Edition 07.2017