Parity control enabled and Odd Parity is selected
Clock Phase
The first clock transition is the first data capture edge
The second clock transition is the first data capture edge
Clock Polarity
Steady low value on SCLK pin outside transmission
window
Steady high value on SCLK pin outside transmission
window
Stop Bits
Wakeup
USART wake up from Mute mode on Idle Line
LL_USART_WAKEUP_ADDRESSMARK
USART wake up from Mute mode on Address
Mark
Exported_Macros_Helper
__LL_USART_DIV_SAMPLING8_100
Description:
Compute USARTDIV value according to
Peripheral Clock and expected Baud Rate
in 8 bits sampling mode (32 bits value of
USARTDIV is returned)
Parameters:
__PERIPHCLK__: Peripheral Clock
frequency used for USART instance
__BAUDRATE__: Baud rate value to
achieve
Return value:
USARTDIV: value to be used for BRR
register filling in OverSampling_8 case
__LL_USART_DIVMANT_SAMPLING8
__LL_USART_DIVFRAQ_SAMPLING8
__LL_USART_DIV_SAMPLING16_100
Description:
Compute USARTDIV value according to
Peripheral Clock and expected Baud Rate
in 16 bits sampling mode (32 bits value of
USARTDIV is returned)
Parameters:
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