In the case of a clock error, the RNG is no more able to
generate random numbers because the PLL48CLK clock is
not correct. User has to check that the clock controller is
correctly configured to provide the RNG clock and clear the
CEIS bit using __HAL_RNG_CLEAR_IT(). The clock error
has no impact on the previously generated random numbers,
and the RNG_DR register contents can be used.
In the case of a seed error, the generation of random
numbers is interrupted as long as the SECS bit is '1'. If a
number is available in the RNG_DR register, it must not be
used because it may not have enough entropy. In this case, it
is recommended to clear the SEIS bit using
__HAL_RNG_CLEAR_IT(), then disable and enable the RNG
peripheral to reinitialize and restart the RNG.
User-written HAL_RNG_ErrorCallback() API is called once
whether SEIS or CEIS are set.
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