Region: This parameter can be one of the following values:
LL_MPU_REGION_NUMBER0
LL_MPU_REGION_NUMBER1
LL_MPU_REGION_NUMBER2
LL_MPU_REGION_NUMBER3
LL_MPU_REGION_NUMBER4
LL_MPU_REGION_NUMBER5
LL_MPU_REGION_NUMBER6
LL_MPU_REGION_NUMBER7
Reference Manual to
LL API cross
reference:
MPU_RNR REGION LL_MPU_DisableRegion
MPU_RASR ENABLE LL_MPU_DisableRegion
52.2 CORTEX Firmware driver defines
52.2.1 CORTEX
MPU Bufferable Access
Bufferable memory attribute
LL_MPU_ACCESS_NOT_BUFFERABLE
Not Bufferable memory attribute
MPU Cacheable Access
Cacheable memory attribute
LL_MPU_ACCESS_NOT_CACHEABLE
Not Cacheable memory attribute
SYSTICK Clock Source
LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AHB clock divided by 8 selected as SysTick
clock source.
LL_SYSTICK_CLKSOURCE_HCLK
AHB clock selected as SysTick clock source.
MPU Control
LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
Disable NMI and privileged SW access
LL_MPU_CTRL_HARDFAULT_NMI
Enables the operation of MPU during hard
fault, NMI, and FAULTMASK handlers
LL_MPU_CTRL_PRIVILEGED_DEFAULT
Enable privileged software access to default
memory map
LL_MPU_CTRL_HFNMI_PRIVDEF
Enable NMI and privileged SW access
Handler Fault type
MPU Instruction Access