69 LL UTILS Generic Driver
69.1 UTILS Firmware driver registers structures
69.1.1 LL_UTILS_PLLInitTypeDef
Data Fields
uint32_t PLLM
uint32_t PLLN
uint32_t PLLP
Field Documentation
uint32_t LL_UTILS_PLLInitTypeDef::PLLM
Division factor for PLL VCO input clock. This parameter can be a value of
RCC_LL_EC_PLLM_DIVThis feature can be modified afterwards using unitary
function LL_RCC_PLL_ConfigDomain_SYS().
uint32_t LL_UTILS_PLLInitTypeDef::PLLN
Multiplication factor for PLL VCO output clock. This parameter must be a number
between Min_Data = 8 and Max_Data = 86This feature can be modified afterwards
using unitary function LL_RCC_PLL_ConfigDomain_SYS().
uint32_t LL_UTILS_PLLInitTypeDef::PLLP
Division for the main system clock. This parameter can be a value of
RCC_LL_EC_PLLP_DIVThis feature can be modified afterwards using unitary
function LL_RCC_PLL_ConfigDomain_SYS().
69.1.2 LL_UTILS_ClkInitTypeDef
Data Fields
uint32_t AHBCLKDivider
uint32_t APB1CLKDivider
uint32_t APB2CLKDivider
Field Documentation
uint32_t LL_UTILS_ClkInitTypeDef::AHBCLKDivider
The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of RCC_LL_EC_SYSCLK_DIVThis feature can be
modified afterwards using unitary function LL_RCC_SetAHBPrescaler().
uint32_t LL_UTILS_ClkInitTypeDef::APB1CLKDivider
The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of RCC_LL_EC_APB1_DIVThis feature can be
modified afterwards using unitary function LL_RCC_SetAPB1Prescaler().
uint32_t LL_UTILS_ClkInitTypeDef::APB2CLKDivider
The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of RCC_LL_EC_APB2_DIVThis feature can be
modified afterwards using unitary function LL_RCC_SetAPB2Prescaler().
69.2 UTILS Firmware driver API description
69.2.1 System Configuration functions
System, AHB and APB buses clocks configuration
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