LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR BKPSRAMLPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR FLITFLPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR SRAM1LPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR SRAM2LPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR BKPSRAMLPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR DMA1LPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR DMA2LPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACLPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACTXLPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACRXLPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACPTPLPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR OTGHSLPEN
LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR OTGHSULPILPEN
LL_AHB1_GRP1_DisableClockLowPower
LL_AHB2_GRP1_EnableClock
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock
(uint32_t Periphs)
Enable AHB2 peripherals clock.
Periphs: This parameter can be a combination of the
following values: (*) value not defined in all devices.
LL_AHB2_GRP1_PERIPH_DCMI (*)
LL_AHB2_GRP1_PERIPH_CRYP (*)
LL_AHB2_GRP1_PERIPH_HASH (*)
LL_AHB2_GRP1_PERIPH_RNG
LL_AHB2_GRP1_PERIPH_OTGFS
Reference Manual to
LL API cross
reference:
AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock
AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock
AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock
AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
LL_AHB2_GRP1_IsEnabledClock
__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock
(uint32_t Periphs)