ARM ARM7TDMI - Page 11

ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. xi
List of Figures
ARM7TDMI Technical Reference Manual
Key to timing diagram conventions .......................................................................... xviii
Figure 1-1 Instruction pipeline .................................................................................................... 1-2
Figure 1-2 ARM7TDMI processor block diagram ....................................................................... 1-8
Figure 1-3 ARM7TDMI main processor logic ............................................................................. 1-9
Figure 1-4 ARM7TDMI processor functional diagram .............................................................. 1-10
Figure 1-5 ARM instruction set formats .................................................................................... 1-12
Figure 1-6 Thumb instruction set formats ................................................................................. 1-21
Figure 2-1 LIttle-endian addresses of bytes and halfwords within words ................................... 2-4
Figure 2-2 Big-endian addresses of bytes and halfwords within words ...................................... 2-5
Figure 2-3 Register organization in ARM state ........................................................................... 2-9
Figure 2-4 Register organization in Thumb state ..................................................................... 2-10
Figure 2-5 Mapping of Thumb-state registers onto ARM-state registers .................................. 2-11
Figure 2-6 Program status register format ................................................................................ 2-13
Figure 3-1 Simple memory cycle ................................................................................................ 3-4
Figure 3-2 Nonsequential memory cycle .................................................................................... 3-6
Figure 3-3 Sequential access cycles .......................................................................................... 3-7
Figure 3-4 Internal cycles ........................................................................................................... 3-8
Figure 3-5 Merged IS cycle ........................................................................................................ 3-9
Figure 3-6 Coprocessor register transfer cycles ....................................................................... 3-10
Figure 3-7 Memory cycle timing ............................................................................................... 3-10
Figure 3-8 Pipelined addresses ................................................................................................ 3-14
Figure 3-9 Depipelined addresses ............................................................................................ 3-15
Figure 3-10 SRAM compatible address timing ........................................................................... 3-16