ARM ARM7TDMI - Page 12

List of Figures
xii Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Figure 3-11 External bus arrangement ...................................................................................... 3-17
Figure 3-12 Bidirectional bus timing ........................................................................................... 3-18
Figure 3-13 Unidirectional bus timing ......................................................................................... 3-18
Figure 3-14 External connection of unidirectional buses ........................................................... 3-19
Figure 3-15 Data write bus cycle ................................................................................................ 3-20
Figure 3-16 Data bus control circuit ........................................................................................... 3-20
Figure 3-17 Test chip data bus circuit ........................................................................................ 3-23
Figure 3-18 Memory access ....................................................................................................... 3-25
Figure 3-19 Two-cycle memory access ..................................................................................... 3-26
Figure 3-20 Data replication ....................................................................................................... 3-28
Figure 3-21 Typical system timing ............................................................................................. 3-30
Figure 3-22 Reset sequence ...................................................................................................... 3-32
Figure 4-1 Coprocessor busy-wait sequence ............................................................................. 4-8
Figure 4-2 Coprocessor register transfer sequence ................................................................... 4-9
Figure 4-3 Coprocessor data operation sequence ................................................................... 4-10
Figure 4-4 Coprocessor load sequence ................................................................................... 4-11
Figure 4-5 Coprocessor connections with bidirectional bus ..................................................... 4-12
Figure 4-6 Coprocessor connections with unidirectional bus ................................................... 4-13
Figure 4-7 Connecting multiple coprocessors .......................................................................... 4-14
Figure 5-1 Typical debug system ............................................................................................... 5-4
Figure 5-2 ARM7TDMI block diagram ........................................................................................ 5-5
Figure 5-3 Debug state entry ..................................................................................................... 5-8
Figure 5-4 Clock switching on entry to debug state ................................................................. 5-11
Figure 5-5 ARM7 CPU main processor logic, TAP controller, and EmbeddedICE-RT logic .... 5-14
Figure 5-6 DCC control register format .................................................................................... 5-17
Figure 7-1 General timings ......................................................................................................... 7-3
Figure 7-2 ABE address control ................................................................................................. 7-5
Figure 7-3 Bidirectional data write cycle .................................................................................... 7-5
Figure 7-4 Bidirectional data read cycle ..................................................................................... 7-6
Figure 7-5 Data bus control ........................................................................................................ 7-7
Figure 7-6 Output 3-state time ................................................................................................... 7-8
Figure 7-7 Unidirectional data write cycle .................................................................................. 7-8
Figure 7-8 Unidirectional data read cycle ................................................................................... 7-9
Figure 7-9 Configuration pin timing ............................................................................................ 7-9
Figure 7-10 Coprocessor timing ................................................................................................. 7-10
Figure 7-11 Exception timing ..................................................................................................... 7-11
Figure 7-12 Synchronous interrupt timing .................................................................................. 7-12
Figure 7-13 Debug timing ........................................................................................................... 7-12
Figure 7-14 DCC output timing .................................................................................................. 7-13
Figure 7-15 Breakpoint timing .................................................................................................... 7-14
Figure 7-16 TCK and ECLK relationship .................................................................................... 7-14
Figure 7-17 MCLK timing ........................................................................................................... 7-15
Figure 7-18 Scan general timing ................................................................................................ 7-16
Figure 7-19 Reset period timing ................................................................................................. 7-17
Figure 7-20 Output enable and disable times due to HIGHZ TAP instruction ............................ 7-17
Figure 7-21 Output enable and disable times due to data scanning .......................................... 7-18
Figure 7-22 ALE address control ............................................................................................... 7-18