List of Figures
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. xiii
Figure 7-23 APE address control ............................................................................................... 7-19
Figure B-1 ARM7TDMI core scan chain arrangements .............................................................. B-4
Figure B-2 Test access port controller state transitions .............................................................. B-5
Figure B-3 ID code register format ............................................................................................ B-14
Figure B-4 Output scan cell ...................................................................................................... B-17
Figure B-5 Clock switching on entry to debug state .................................................................. B-22
Figure B-6 Debug exit sequence .............................................................................................. B-28
Figure B-7 EmbeddedICE-RT block diagram ........................................................................... B-43
Figure B-8 Watchpoint control value and mask format ............................................................. B-45
Figure B-9 Debug control register format .................................................................................. B-51
Figure B-10 Debug status register format ................................................................................... B-54
Figure B-11 Debug control and status register structure ............................................................ B-55
Figure B-12 Debug abort status register ..................................................................................... B-56
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