Signal and Transistor Descriptions
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. A-9
nENOUT
Not enable output
O During a write cycle, this signal is driven LOW before the rising edge of
MCLK, and remains LOW for the entire cycle. This can be used to aid
arbitration in shared bus applications.
See Chapter 3 Memory Interface.
nENOUTI
Not enable output
O During a coprocessor register transfer C-cycle from the EmbeddedICE-RT
communications channel coprocessor to the ARM core, this signal goes
LOW. This can be used to aid arbitration in shared bus systems.
nEXEC
Not executed
O This is HIGH when the instruction in the execution unit is not being executed
because, for example, it has failed its condition code check.
nFIQ
Not fast interrupt request
IC Taking this LOW causes the processor to be interrupted if the appropriate
enable in the processor is active. The signal is level-sensitive and must be
held LOW until a suitable response is received from the processor. nFIQ can
be synchronous or asynchronous to MCLK, depending on the state of
ISYNC.
nHIGHZ
Not HIGHZ
O When the current instruction is HIGHZ this signal is LOW. This is used to
place the scan cells of that scan chain in the high impedance state.
This must be left unconnected, if an external boundary-scan chain is not
connected.
nIRQ
Not interrupt request
IC As nFIQ, but with lower priority. Can be taken LOW to interrupt the
processor when the appropriate enable is active. nIRQ can be synchronous
or asynchronous, depending on the state of ISYNC.
nM[4:0]
Not processor mode
O These are the inverse of the internal status bits indicating the current
processor mode.
nMREQ
Not memory request
O When the processor requires memory access during the following cycle this
is LOW.
nOPC
Not op-code fetch
O When the processor is fetching an instruction from memory this is LOW.
This is one of the signals controlled by APE, ALE, and ABE.
Table A-3 Signal descriptions (continued)
Name Type Description
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