ARM ARM7TDMI - Page 34

Introduction
1-14 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Test equivalence TEQ{cond} Rn, <Oprnd2>
AND AND{cond}{S} Rd, Rn, <Oprnd2>
EOR EOR{cond}{S} Rd, Rn, <Oprnd2>
ORR ORR{cond}{S} Rd, Rn, <Oprnd2>
Bit clear BIC{cond}{S} Rd, Rn, <Oprnd2>
Branch Branch B{cond} label
Branch with link BL{cond} label
Branch and exchange instruction set BX{cond} Rn
Load Word LDR{cond} Rd, <a_mode2>
Word with user-mode privilege LDR{cond}T Rd, <a_mode2P>
Byte LDR{cond}B Rd, <a_mode2>
Byte with user-mode privilege LDR{cond}BT Rd, <a_mode2P>
Byte signed LDR{cond}SB Rd, <a_mode3>
Halfword LDR{cond}H Rd, <a_mode3>
Halfword signed LDR{cond}SH Rd, <a_mode3>
Multiple block data operations -
• Increment before
LDM{cond}IB Rd{!}, <reglist>{^}
• Increment after LDM{cond}IA Rd{!}, <reglist>{^}
• Decrement before LDM{cond}DB Rd{!}, <reglist>{^}
• Decrement after LDM{cond}DA Rd{!}, <reglist>{^}
• Stack operation LDM{cond}<a_mode4L> Rd{!}, <reglist>
• Stack operation, and restore CPSR LDM{cond}<a_mode4L> Rd{!}, <reglist+pc>^
• Stack operation with user registers LDM{cond}<a_mode4L> Rd{!}, <reglist>^
Store Word STR{cond} Rd, <a_mode2>
Word with user-mode privilege STR{cond}T Rd, <a_mode2P>
Table 1-2 ARM instruction summary (continued)
Operation Assembly syntax