ARM ARM7TDMI - Page 35

Introduction
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 1-15
Addressing modes
The addressing modes are procedures shared by different instructions for generating
values used by the instructions. The five addressing modes used by the ARM7TDMI
processor are:
Mode 1 Shifter operands for data processing instructions.
Mode 2 Load and store word or unsigned byte.
Mode 3 Load and store halfword or load signed byte.
Mode 4 Load and store multiple.
Mode 5 Load and store coprocessor.
Byte STR{cond}B Rd, <a_mode2>
Byte with user-mode privilege STR{cond}BT Rd, <a_mode2P>
Halfword STR{cond}H Rd, <a_mode3>
Multiple block data operations -
• Increment before
STM{cond}IB Rd{!}, <reglist>{^}
• Increment after STM{cond}IA Rd{!}, <reglist>{^}
• Decrement before STM{cond}DB Rd{!}, <reglist>{^}
• Decrement after STM{cond}DA Rd{!}, <reglist>{^}
• Stack operation STM{cond}<a_mode4S> Rd{!}, <reglist>
• Stack operation with user registers STM{cond}<a_mode4S> Rd{!}, <reglist>^
Swap Word SWP{cond} Rd, Rm, [Rn]
Byte SWP{cond}B Rd, Rm, [Rn]
Coprocessors Data operation CDP{cond} p<cpnum>, <op1>, CRd, CRn, CRm, <op2>
Move to ARM register from coprocessor MRC{cond} p<cpnum>, <op1>, Rd, CRn, CRm, <op2>
Move to coprocessor from ARM register MCR{cond} p<cpnum>, <op1>, Rd, CRn, CRm, <op2>
Load LDC{cond} p<cpnum>, CRd, <a_mode5>
Store STC{cond} p<cpnum>, CRd, <a_mode5>
Software interrupt SWI 24bit_Imm
Table 1-2 ARM instruction summary (continued)
Operation Assembly syntax