ARM ARM7TDMI - Page 43

Introduction
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. 1-23
EOR EOR Rd, Rs
OR ORR Rd, Rs
Bit clear BIC Rd, Rs
Move NOT MVN Rd, Rs
Test bits TST Rd, Rs
Shift/Rotate Logical shift left LSL Rd, Rs, #5bit_shift_imm LSL Rd, Rs
Logical shift right LSR Rd, Rs, #5bit_shift_imm LSR Rd, Rs
Arithmetic shift right ASR Rd, Rs, #5bit_shift_imm ASR Rd, Rs
Rotate right ROR Rd, Rs
Branch Conditional -
•if Z set
BEQ label
• if Z clear BNE label
•if C set BCS label
• if C clear BCC label
•if N set BMI label
•if N clear BPL label
•if V set BVS label
•if V clear BVC label
• if C set and Z clear BHI label
• if C clear and Z set BLS label
• if ((N set and V set) or (N clear and V clear)) BGE label
• if ((N set and V clear) or if (N clear and V set)) BLT label
• if (Z clear and ((N or V set) or (N or V clear))) BGT label
• if (Z set or ((N set and V clear) or (N clear and
V set)))
BLE label
Table 1-7 Thumb instruction set summary (continued)
Operation Assembly syntax