ARM ARM7TDMI - Page 44

Introduction
1-24 Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Unconditional B label
Long branch with link BL label
Optional state change -
• to address held in Lo reg
BX Rs
• to address held in Hi reg BX Hs
Load With immediate offset -
• word
LDR Rd, [Rb, #7bit_offset]
• halfword LDRH Rd, [Rb, #6bit_offset]
• byte LDRB Rd, [Rb, #5bit_offset]
With register offset -
• word
LDR Rd, [Rb, Ro]
• halfword LDRH Rd, [Rb, Ro]
• signed halfword LDRSH Rd, [Rb, Ro]
• byte LDRB Rd, [Rb, Ro]
• signed byte LDRSB Rd, [Rb, Ro]
PC-relative LDR Rd, [PC, #10bit_Offset]
SP-relative LDR Rd, [SP, #10bit_Offset]
Address -
• using PC
ADD Rd, PC, #10bit_Offset
• using SP ADD Rd, SP, #10bit_Offset
Multiple
LDMIA Rb!, <reglist>
Store With immediate offset -
• word
STR Rd, [Rb, #7bit_offset]
• halfword STRH Rd, [Rb, #6bit_offset]
• byte STRB Rd, [Rb, #5bit_offset]
Table 1-7 Thumb instruction set summary (continued)
Operation Assembly syntax