ARM ARM7TDMI - Page 7

ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. vii
List of Tables
ARM7TDMI Technical Reference Manual
Change history .............................................................................................................. ii
Table 1-1 Key to tables ........................................................................................................... 1-11
Table 1-2 ARM instruction summary ....................................................................................... 1-13
Table 1-3 Addressing modes .................................................................................................. 1-16
Table 1-4 Operand 2 ............................................................................................................... 1-18
Table 1-5 Fields ....................................................................................................................... 1-19
Table 1-6 Condition fields ........................................................................................................ 1-19
Table 1-7 Thumb instruction set summary .............................................................................. 1-22
Table 2-1 Register mode identifiers .......................................................................................... 2-7
Table 2-2 PSR mode bit values ............................................................................................... 2-15
Table 2-3 Exception entry and exit .......................................................................................... 2-16
Table 2-4 Exception vectors .................................................................................................... 2-21
Table 2-5 Exception priority order ........................................................................................... 2-22
Table 3-1 Bus cycle types ......................................................................................................... 3-5
Table 3-2 Burst types ................................................................................................................ 3-7
Table 3-3 Significant address bits ........................................................................................... 3-12
Table 3-4 nOPC ...................................................................................................................... 3-12
Table 3-5 nTRANS encoding .................................................................................................. 3-13
Table 3-6 Tristate control of processor outputs ....................................................................... 3-21
Table 3-7 Read accesses ........................................................................................................ 3-27
Table 3-8 Use of nM[4:0] to indicate current processor mode ................................................ 3-31
Table 4-1 Coprocessor availability ............................................................................................ 4-3
Table 4-2 Handshaking signals ................................................................................................. 4-6