ARM ARM7TDMI - Page 8

List of Tables
viii Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Table 4-3 Summary of coprocessor signaling ........................................................................... 4-7
Table 4-4 Mode identifier signal meanings, nTRANS ............................................................. 4-17
Table 5-1 DCC register access instructions ............................................................................ 5-18
Table 6-1 Branch instruction cycle operations .......................................................................... 6-4
Table 6-2 Thumb long branch with link ..................................................................................... 6-5
Table 6-3 Branch and exchange instruction cycle operations .................................................. 6-6
Table 6-4 Data operation instruction cycles .............................................................................. 6-8
Table 6-5 Multiply instruction cycle operations ......................................................................... 6-9
Table 6-6 Multiply accumulate instruction cycle operations ...................................................... 6-9
Table 6-7 Multiply long instruction cycle operations ............................................................... 6-10
Table 6-8 Multiply accumulate long instruction cycle operations ............................................ 6-10
Table 6-9 Load register instruction cycle operations .............................................................. 6-12
Table 6-10 MAS[1:0] signal encoding ....................................................................................... 6-13
Table 6-11 Store register instruction cycle operations .............................................................. 6-14
Table 6-12 Load multiple registers instruction cycle operations ............................................... 6-15
Table 6-13 Store multiple registers instruction cycle operations ............................................... 6-17
Table 6-14 Data swap instruction cycle operations .................................................................. 6-18
Table 6-15 Software Interrupt instruction cycle operations ....................................................... 6-19
Table 6-16 Coprocessor data operation instruction cycle operations ....................................... 6-20
Table 6-17 Coprocessor data transfer instruction cycle operations .......................................... 6-21
Table 6-18 coprocessor data transfer instruction cycle operations ........................................... 6-23
Table 6-19 Coprocessor register transfer, load from coprocessor ............................................ 6-25
Table 6-20 Coprocessor register transfer, store to coprocessor ............................................... 6-26
Table 6-21 Undefined instruction cycle operations ................................................................... 6-27
Table 6-22 Unexecuted instruction cycle operations ................................................................ 6-28
Table 6-23 ARM instruction speed summary ............................................................................ 6-29
Table 7-1 General timing parameters ....................................................................................... 7-4
Table 7-2 ABE address control timing parameters ................................................................... 7-5
Table 7-3 Bidirectional data write cycle timing parameters ....................................................... 7-6
Table 7-4 Bidirectional data read cycle timing parameters ....................................................... 7-6
Table 7-5 Data bus control timing parameters .......................................................................... 7-7
Table 7-6 Output 3-state time timing parameters ..................................................................... 7-8
Table 7-7 Unidirectional data write cycle timing parameters .................................................... 7-8
Table 7-8 Unidirectional data read cycle timing parameters ..................................................... 7-9
Table 7-9 Configuration pin timing parameters ....................................................................... 7-10
Table 7-10 Coprocessor timing parameters .............................................................................. 7-10
Table 7-11 Exception timing parameters .................................................................................. 7-11
Table 7-12 Synchronous interrupt timing parameters ............................................................... 7-12
Table 7-13 Debug timing parameters ....................................................................................... 7-13
Table 7-14 DCC output timing parameters ............................................................................... 7-13
Table 7-15 Breakpoint timing parameters ................................................................................. 7-14
Table 7-16 TCK and ECLK timing parameters ......................................................................... 7-15
Table 7-17 MCLK timing parameters ........................................................................................ 7-15
Table 7-18 Scan general timing parameters ............................................................................. 7-16
Table 7-19 Reset period timing parameters .............................................................................. 7-17
Table 7-20 Output enable and disable timing parameters ........................................................ 7-18
Table 7-21 ALE address control timing parameters .................................................................. 7-19