Chapter 4 INTERFACE SETTINGS
137
[7] MODE6 (Octal Link ) (split vertically into 2 + no dividing in each board <3>)
(Cross Mode))
Channels 1 to 8 are used. The screen is split vertically into 2 and output from each board. CH1-4 outputs the left
half. CH5-8 outputs the right half with the below pixel assignment.
Given here as an example of the resolution is 4096 × 2048, the dot clock frequency is 1184 MHz with the 10 bits
output.
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[9:0]
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[9:0]
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[9:0]
・・・
[9:0]
・・・
[9:0]
・・・
[9:0]
・・・
[9:0]
・・・
[9:0]
・・・
L0~L2159
L0~L2159
L0~L2159
L0~L2159
L0~L2159
L0~L2159
L0~L2159
L0~L2159
CLK
148MHz
1CH
2CH
3CH
4CH
5CH
6CH
7CH
8CH
D 0
D 1
D 4
D 5
D 2048
D 2049
D 2052
D 2053
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
D 2
D 3
D 6
D 7
D 2050
D 2051
D 2054
D 2055
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
D 8
D 9
D 12
D 13
D 2056
D 2057
D 2060
D 2061
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
D 10
D 11
D 14
D 15
D 2058
D 2059
D 2062
D 2063
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
D 2032
D 2033
D 2036
D 2037
D 4080
D 4081
D 4084
D 4085
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
D 2034
D 2035
D 2038
D 2039
D 4082
D 4083
D 4086
D 4087
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
D 2040
D 2041
D 2044
D 2045
D 4088
D 4089
D 4092
D 4093
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
D 2042
D 2043
D 2046
D 2047
D 4090
D 4091
D 4094
D 4095
5CH 6CH 7CH 8CH
1CH 2CH 3CH 4CH