4 CIRCUIT BREAKER FAIL PROTECTION
When a fault occurs, one or more protection devices will operate and issue a trip command to the relevant
circuit breakers. Operation of the circuit breaker is essential to isolate the fault and prevent, or at least limit,
damage to the power system. For transmission and sub-transmission systems, slow fault clearance can also
threaten system stability.
For these reasons, it is common practise to install Circuit Breaker Failure protection (CBF). CBF protection
monitors the circuit breaker and establishes whether it has opened within a reasonable time. If the fault
current has not been interrupted following a set time delay from circuit breaker trip initiation, the CBF
protection will operate, whereby the upstream circuit breakers are back-tripped to ensure that the fault is
isolated.
CBF operation can also reset all start output contacts, ensuring that any blocks asserted on upstream
protection are removed.
4.1 CIRCUIT BREAKER FAIL IMPLEMENTATION
Circuit Breaker Failure Protection is implemented in the CB FAIL & I< column of the relevant settings group.
Circuit breaker failure protection (CBF) uses logic to combine internally and externally generated trip signals
with current measurements and timers. Following a fault, if a circuit breaker has not operated, signals to
isolate the fault and the faulty circuit breaker are asserted.
By default, CBF is enabled. If you don’t want to use it,in the CONFIGURATION column set CB Fail to
Disabled.
If CBF is set to Enabled
and a fault occurs, the CBF sequence is initiated.
CBF is configured using a combination of:
● settings contained in the CB FAIL column of the relevant settings group
● mapping signals in the Programmable Scheme Logic (PSL).
Use CBF Control By to set the CBF reset condition. You can choose to reset if the I< Current Set threshold
is satisfied, you can choose to reset if a 52a contact indicates that the circuit breaker has operated correctly,
or you can use a combination of both.
The undercurrent reset element operates in less than one cycle.
The CBF has four timers. Two are used for a CBF that is initiated by internal protection. These are CB Fail 1
Timer (tBF1) and CB Fail 2 Timer (tBF2). The other two are used for a CBF that is initiated by external
protection. These are CB Fail 3 Timer (tBF3) and CB Fail 4 Timer (tBF4).
There is an overcurrent element that can be enabled to provide an additional input to the CBF logic.
The settings are common to all terminals in the scheme but the CBF logic is applied individually at each
terminal according to the specific terminal conditions.
Tripping for CBF conditions tries to minimise disruption to the system by monitoring the topology and
adapting the tripping decision to changing configurations.
4.2 CIRCUIT BREAKER FAIL LOGIC
The following diagram shows CBF logic for internally indicated faults. The digital input and output signals
(DDBs) that need mapping in the PSL are:
● Int CBF Init Tn (n=1-18)
● CBF Retrip Tn (n=1-18)
● CBF Bktrip Zn (n=1-4)
MiCOM P747 Chapter 5 - Protection Functions
P747-TM-EN-1 111
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