Table of Figures
Figure 1: Functional Overview 9
Figure 2: Hardware architecture 26
Figure 3: Exploded view of IED 27
Figure 4: Front panel (80TE) 29
Figure 5: Rear view of populated 80TE case 33
Figure 6: Terminal block types 34
Figure 7: Rear connection to terminal block 35
Figure 8: Main processor board 36
Figure 9: Combined coprocessor and isolated digital input board 37
Figure 10: Power supply board 38
Figure 11: Power Supply Assembly 39
Figure 12: Power Supply Terminals 40
Figure 13: Watchdog contact terminals 41
Figure 14: Rear serial port terminals 42
Figure 15: Input Module - 1 transformer board 42
Figure 16: Input module schematic 43
Figure 17: Instrument Transformer board 45
Figure 18: Main input board 46
Figure 19: Output relay board - 8 contacts 47
Figure 20: IRIG-B board 49
Figure 21: Fibre optic board 50
Figure 22: Rear communication board 51
Figure 23: Ethernet board 52
Figure 24: Redundant Ethernet board 53
Figure 25: Menu navigation 59
Figure 26: Default display navigation 61
Figure 27: Current Differential Protection 100
Figure 28: Compensation using biased differential characteristic 102
Figure 29: Multiple tripping criteria 103
Figure 30: Topology replica function 104
Figure 31: Zone tripping characteristic. 106
Figure 32: Check zone supervision characteristic. 107
Figure 33: Circuitry check characteristic. 108
Figure 34: Example of busbar dead-zone 110
Figure 35: Dead-zone logic 110
Figure 36: CBF initiated by internal signal 112
Figure 37: CBF initiated by external signal 113
Figure 38: Busbar topology used in configuration example. 137