Intel Cyclone 10 GX User Manual

6. Create a transceiver reset controller. You can use your own reset controller or use
the Intel Cyclone 10 GX Transceiver Native PHY Reset Controller IP.
7. Connect the Intel Cyclone 10 GX Transceiver Native PHY to the PLL IP and the
reset controller.
Figure 48. Connection Guidelines for a 10GBASE-R with IEEE 1588v2 PHY Design
Reset
Controller
To MAC/RS
through XGMII
Interface
64d + 8c
64d + 8c
FIFO in the
FPGA core
for TX
FIFO in the
FPGA core
for RX
PLL IP
Medium
Cyclone 10 Transceiver
Native PHY
8. Simulate your design to verify its functionality.
2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R and 10GBASE-R with
IEEE 1588v2
This section contains the recommended parameter values for this protocol. Refer to
Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of
parameter values.
Table 89. General and Datapath Parameters
The first two sections of the Transceiver Native PHY parameter editor provide a list of general and datapath
options to customize the transceiver.
Parameter
Range
Message level for rule violations error, warning
Transceiver Configuration Rule 10GBASE-R
10GBASE-R 1588
Transceiver mode TX / RX Duplex, TX Simplex, RX Simplex
Number of data channels 1 to 12
Data rate 10312.5 Mbps
Enable datapath and interface reconfiguration Off
Enable simplified data interface On
Off
Table 90. TX PMA Parameters
Parameter Range
TX channel bonding mode Not bonded
TX local clock division factor 1, 2, 4, 8
Number of TX PLL clock inputs per channel 1, 2, 3, 4
Initial TX PLL clock input selection 0, 1, 2, 3
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English