Intel Cyclone 10 GX User Manual

Table 91. RX PMA Parameters
Parameter Range
Number of CDR reference clocks 1 to 5
Selected CDR reference clock 0 to 4
Selected CDR reference clock frequency 322.265625 MHz and 644.53125 MHz
PPM detector threshold 100, 300, 500, 1000
CTLE adaptation mode manual
Table 92. Enhanced PCS Parameters
Parameter Range
Enhanced PCS/PMA interface width 32, 40, 64
FPGA fabric/Enhanced PCS interface width 66
Enable Enhanced PCS low latency mode On
Off
Enable RX/TX FIFO double-width mode Off
TX FIFO mode • Phase Compensation (10GBASE-R)
• Register or Fast register (10GBASE-R with 1588)
TX FIFO partially full threshold 11
TX FIFO partially empty threshold 2
RX FIFO mode • 10GBASE-R (10GBASE-R)
• Register (10GBASE-R with 1588)
RX FIFO partially full threshold 23
RX FIFO partially empty threshold 2
Table 93. 64B/66B Encoder and Decoder Parameters
Parameter Range
Enable TX 64B/66B encoder On
Enable RX 64B/66B decoder On
Enable TX sync header error insertion On
Off
Table 94. Scrambler and Descrambler Parameters
Parameter Range
Enable TX scrambler (10GBASE-R / Interlaken) On
TX scrambler seed (10GBASE-R / Interlaken) 0x03ffffffffffffff
Enable RX descrambler (10GBASE-R / Interlaken) On
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
105

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English