Index - 8
15.5.15 Cautions ........................................................................................................................... 469
15.5.16 Communication operations ............................................................................................... 470
15.5.17 Timing of I
2
C interrupt request (INTIICAn) occurrence ..................................................... 478
15.6 Timing Charts ....................................................................................................................... 499
16. DATA TRANSFER CONTROLLER (DTC) .................................................................................. 514
16.1 Functions of DTC .................................................................................................................. 514
16.2 Configuration of DTC ............................................................................................................ 516
16.3 Registers Controlling DTC .................................................................................................... 517
16.3.1 Allocation of DTC Control Data Area and DTC Vector Table Area ................................... 518
16.3.2 Control Data Allocation ..................................................................................................... 519
16.3.3 Vector Table ...................................................................................................................... 520
16.3.4 Peripheral enable register 1 (PER1) ................................................................................. 522
16.3.5 DTC control register j (DTCCRj) (j = 0 to 23) .................................................................... 523
16.3.6 DTC block size register j (DTBLSj) (j = 0 to 23) ................................................................ 524
16.3.7 DTC transfer count register j (DTCCTj) (j = 0 to 23) ......................................................... 524
16.3.8 DTC transfer count reload register j (DTRLDj) (j = 0 to 23) .............................................. 525
16.3.9 DTC source address register j (DTSARj) (j = 0 to 23) ...................................................... 525
16.3.10 DTC destination address register j (DTDARj) (j = 0 to 23) ............................................... 525
16.3.11 DTC activation enable register i (DTCENi) (i = 0 to 4) ...................................................... 526
16.3.12 DTC base address register (DTCBAR) ............................................................................ 529
16.4 DTC Operation ..................................................................................................................... 529
16.4.1 Activation Sources ............................................................................................................ 530
16.4.2 Normal Mode .................................................................................................................... 531
16.4.3 Repeat Mode .................................................................................................................... 532
16.4.4 Chain Transfers ................................................................................................................ 534
16.5 Cautions for DTC .................................................................................................................. 535
16.5.1 Setting DTC Control Data and Vector Table ..................................................................... 535
16.5.2 Allocation of DTC Control Data Area and DTC Vector Table Area ................................... 535
16.5.3 DTC Pending Instruction .................................................................................................. 536
16.5.4 Operation when Accessing Data Flash Memory Space .................................................... 536
16.5.5 Number of DTC Execution Clock Cycles .......................................................................... 537
16.5.6 DTC Response Time ........................................................................................................ 538
16.5.7 DTC Activation Sources ................................................................................................... 538
16.5.8 Operation in Standby Mode Status ................................................................................... 539
17. EVENT LINK CONTROLLER (ELC) ........................................................................................... 540
17.1 Functions of ELC .................................................................................................................. 540
17.2 Configuration of ELC ............................................................................................................ 540
17.3 Registers Controlling ELC .................................................................................................... 541
17.3.1 Event output destination select register n (ELSELRn) (n = 00, 03, 04, 07, 13, 16 to 23) . 541
17.4 ELC Operation ...................................................................................................................... 543
18. RF TRANSCEIVER .................................................................................................................... 544
18.1 RF Transceiver Overview ..................................................................................................... 545
18.2 Pin Functions ........................................................................................................................ 546
18.2.1 Digital pin .......................................................................................................................... 546
18.2.2 Analog pin ......................................................................................................................... 547
18.2.3 Description of RF pin functions ......................................................................................... 547
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